In recent years, programmable logic devices, especially FPGAs (Field Programmable Gate Arrays) have been frequently used in control and communication fields. The FPGA includes an arithmetic operation circuit formed by combining circuit blocks such as basic logic blocks (also referred to as CLBs (Configurable Logic Blocks), LEs (Logic Elements) or the like) in accordance with configuration information loaded into a configuration memory in the FPGA. The FPGA can form various arithmetic operation circuits ranging from a circuit performing a simple numerical operation to a circuit having a function equivalent to a CPU (Central Processing Unit) (for example, see Patent Literature 1).
In the FPGA, one arithmetic operation for achieving the arithmetic operation function is performed by one corresponding circuit block, and various arithmetic operation functions are provided by changing a combination of the circuit blocks. Thus, in the FPGA, as the number of arithmetic operations of the arithmetic operation functions is increased, the number of circuit blocks used in the arithmetic operation circuit is increased. As a result, a complex arithmetic operation circuit with many circuit blocks is formed in the FPGA. This results in increasing the number of circuit elements such as an AND gate, and an OR gate in the circuit block that is used in the arithmetic operation circuit as the number of circuit blocks used in the arithmetic operation circuit is increased.
The circuit elements such as an AND gate, and an OR gate may cause malfunctions due to charged particles or the like in the atmosphere. In a case where the circuit elements incorporated into the arithmetic operation circuit malfunction, for example, the arithmetic operation result of the arithmetic operation circuit is in error. Thus, in the FPGA, as the number of circuit elements used in the arithmetic operation circuit is increased, the probability of being influenced by the charged particles or the like in the atmosphere becomes correspondingly higher, and the possibility of occurrence of an error becomes higher.
In the above-described FPGA, it is known that robustness with respect to the fluctuation of a clock for driving the FPGA, the voltage fluctuation of a voltage source of the FPGA and the temperature fluctuation of the FPGA itself is influenced by a state of route connecting between circuit blocks (connection state), for example, and an error may occur easily depending on the connection state between the circuit blocks included in the arithmetic operation circuit.
Conventionally, it is considered that arithmetic operation circuits each being formed by combining the same type of circuit blocks to perform the same arithmetic processing are provided in duplicate or triplicate form in the FPGA, and thus redundant arithmetic operation circuits simultaneously perform the same arithmetic operation to perform an error verification method for comparing the arithmetic operation results of the arithmetic operation circuits to verify whether a malfunction of the circuit block is caused in any of arithmetic operation circuits, or whether an error occurs in the result of the arithmetic operation.